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3.3.1
C VREG Failure Detection
The digital supply voltage regulator is designed to be unstable with low capacitance. If the connection to the V REG capacitor
becomes open, the digital supply voltage will oscillate and cause either an under voltage, or over voltage failure within one inter-
nal sample time. This failure will result in one of the following:
1. The DEVRES flag in the DEVSTAT register will be set. The device will respond to SPI acceleration requests as defined
in Table 30 .
2. The device will be held in RESET and be non-responsive to SPI requests.
3.3.2
C VREGA Failure Detection
The analog supply voltage regulator is designed to be unstable with low capacitance. If the connection to the V REGA capacitor
becomes open, the analog supply voltage will oscillate and cause either an under voltage, or over voltage failure within one in-
ternal sample time. The DEVRES flag in the DEVSTAT register will be set. The device will respond to SPI acceleration requests
as defined in Table 30 .
3.3.3
V SS and V SSA Ground Loss Monitor
The device detects the loss of ground connection to either V SS or V SSA . A loss of ground connection to V SS will result in a
V REG overvoltage failure. A loss of ground connection to V SSA will result in a V REG undervoltage failure. Both failures result in a
device reset.
3.3.4
SPI Initiated Reset
In addition to voltage monitoring, a device reset can be initiated by a specific series of three write operations involving the
RES_1 and RES_0 bits in the DEVCTL register. Reference Section 3.1.5.1 . for details regarding the SPI initiated reset.
3.4
Internal Oscillator
The device includes a factory trimmed oscillator as specified in Section 2.7 .
3.4.1
Oscillator Monitor
The COUNT register in the customer accessible array is a read-only register which provides the current value of a free-running
8-bit counter derived from the primary oscillator. A 10-bit pre-scaler divides the primary oscillator by 1024. Thus, the value in the
COUNT register increases by one count every 128 μ s, and the register rolls over every 32.768 ms. The SPI master can period-
ically read the COUNT register, and verify the difference between subsequent register reads against the system time base.
1. The SPI access rates and deviations must be taken into account for this oscillator verification method.
3.4.2
CRC Based Clock Monitor
The device includes unique DSP cores for the X-Axis and Y-Axis. Each DSP core uses multiple frequencies derived from the
oscillator, ranging from the base oscillator frequency to the base oscillator frequency divided by 256. In order to guarantee that
the clocks for the two DSP cores are synchronized, a clock CRC monitor is employed. The CRC monitor is updated every cycle
of the base oscillator.
3.5
Transducer
ω n
s + 2 ? ξ ? ω n ? s + ω n
The transducer is an overdamped mass-spring-damper system described by the following transfer function:
2
H ( s ) = ------------------------------------------------------
2 2
where:
ζ = Damping Ratio
ω n = Natural Frequency = 2 ?Π? f n
Reference Section 2.4 for transducer parameters.
MMA65xx
Sensor
Freescale Semiconductor, Inc.
23
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